1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to a low consumption boosted voltage driving circuit for a memory device.
2. Description of Related Art
In the last few years, memory development has been oriented to fulfilling technological requirements of portable devices such as personal computers, mobile telephones, and other devices with even smaller dimensions (e.g., "smart cards"). As a result, memory design has developed towards increasing cell array dimensions while simultaneously reducing energy consumption. A reduction in energy consumption is primarily obtained by decreasing the supply voltage and providing special circuits in the memory device to raise the operating voltage for those instances where it is required for specific functional reasons (e.g., compensation of voltage drops due to the threshold voltages of transistors controlling the memory cells and to ensure required switching speeds).
One such special circuit is a selection circuit for a word line or bit line of an integrated circuit memory device. The selection circuit has a final stage receiving a boosted voltage that is to be transferred to the line or word line selected by the line decoder, or to the gates of the selection transistors of the columns or bit lines selected by the column decoder. The final selection stage is driven by a logic signal from a digital circuit such as the decoder described above to supply an output signal having the level of the boosted voltage. Therefore, the final stage should have a special structure that is fast and congruent from a functional standpoint, such as is present in a typical inverter circuit.
FIGS. 1 and 2 show conventional driving circuits. The driving circuit 1 of FIG. 1 is a classic driving circuit, and the driving circuit 2 of FIG. 2 is a modified embodiment of the driving circuit 1 of FIG. 1. In the driving circuit 1 of FIG. 1, a NAND gate ND receives word line addresses L, M, and N. At the output of the gate ND, an insulating transistor M4 is provided such that its gate, which is maintained at the supply voltage VDD, separates the output of the gate ND from a node A that is connected to the gate of a P-channel MOS transistor M1. The source of the transistor M1 is connected to a boosted voltage VB. In order to express rated values, if the supply voltage VDD is 3.3 volts, the boosted voltage VB generated by boot-strap or internal generator techniques can be 5 volts (i.e., the boosted voltage is higher than the supply voltage VDD by at least the threshold voltage of a MOS transistor).
The drain of transistor M1 is connected to the drain of an N-channel MOS transistor M2 at a node B, and the gate of transistor M2 is connected to node A. As a result, the transistors M1 and M2 form a typical inverter that is supplied by the boosted voltage VB, with node B being the driving output for a word line WL. Further, another P-channel MOS transistor M3 has its gate connected to node B, its source connected to the boosted voltage VB, and its drain connected to node A. When inputs L, M, and N of the gate ND are all at "1" (i.e., for a selected word line), the boosted voltage VB is transferred to the driving output for the word line WL. In such an event, the gate ND output is at "0" and node A of the circuit 1 is discharged to "0". As a result, the transistor M1 is conductive and the transistor M2 is off. Under such conditions, the transistor M3 is also inhibited so as to not be in conflict with the NMOS transistors of the gate ND.
When deselecting the word line, the gate ND charges node A to a voltage equal to the supply voltage VDD less the threshold voltage VT of transistor M4. Thus, transistor M1 is partially off and transistor M2 is fully conducting. The capacity C associated with the word line then starts to discharge itself. During this phase, the transistor M3 begins to enter the conductive state to complete the charge of node A to the boosted voltage VB and fully inhibit transistor M1. The insulating transistor M4, which is preferably a natural transistor (i.e., a transistor with a lower threshold voltage), is used to separate the low voltage or logic portion from the high or boosted voltage portion of the circuit.
For the transistors dimensions, the following considerations apply. With Kp indicating the gain of a P-channel transistor in a hypothetical CMOS inverter that is supplied with the boosted voltage VB (which allows a certain preset selection time for the word line WL) and with Kn indicating the gain of an N-channel transistor in the same hypothetical inverter circuit (which allows a certain preset deselection time), in order to optimize switching time in the driving circuit 1, transistor M1 should have a gain of Kp and transistor M2 a gain of 7 Kn/3. Further, transistor M3 should have a gain of Kp/6 because it supplies the smallest current required for switching completion.
Accordingly, the driving circuit 1 of FIG. 1 can be seen as an inverter with added positive feedback to help completion of the switching process that is started by the low voltage logic. Like an inverter, such a circuit only shows consumption during switching. However, the demand for increasing the memory size has led to an increment in the capacitive loads exhibited by both the word lines and bit lines of an array. Thus, for speed reasons, both transistors M1 and M2 have to be sized according to W/L ratios (i.e., channel width to length ratios) on the order of hundreds. Thus, there is a higher dynamic current consumption, with the average current consumed by the boosted voltage VB at each read cycle being equal to the sum of two terms as shown in the following equation. EQU I=C(VB/T.sub.acc)+I.sub.diss (1)
With capacitive loads C on the order of picofarads and access times T.sub.acc on the order of 100 nanoseconds, the dissipative term I.sub.diss shows an amplitude comparable with that of the first term representing the most effective term. This entails at least two significant results: oversizing the booster circuit, with a consequent consumption of the silicon area; and an additional term of supply current consumption k by I.sub.diss, where k is the booster efficiency. The driving circuit 2 of FIG. 2 is an improvement over the circuit of FIG. 1. In FIG. 2, the gate of transistor M2 is connected upstream of the insulation transistor M4, not downstream as in the circuit of FIG. 1. As a result, the cut-off of transistor M2 is faster during the deselection phase because it is directly driven by the output of the gate ND.